1. Field of the Invention
The present invention relates to a method for conducting an over-erased correction, and more particularly, to a method using Fowler-Nordheim (FN) tunneling and hot carrier soft program to narrow the threshold distribution of the over-erased cells.
2. Description of the Related Art
When a flash memory is erased, it is possible that its threshold voltage becomes too low. Over-erase means a bit line leakage of a memory cell exists in the flash memory. If such memory cell is erased again, it may cause a deep over-erase, which is unrecoverable. Normally, over-erased cells induce bit line leakage during read operation, resulting a loss of “0” reading margin. On the other hand, over-erased cells cause under-erased cells, resulting in a loss of reading ‘1’ margin. FIG. 1 shows a hint diagram in which over-erased cells cause under-erased bits. During a programming operation, over-erased cells induce a large bit line leakage current, causing bit line voltage to drop and reducing the programming efficiency. Therefore, it is important during flash memory operations to prevent occurrence of over-erase events.
The traditional over-erase correction method that uses a drain avalanche hot carrier (DAHC) injection for memory cells is not efficient due to excessive long time and excessive power consumption at high temperature and low operating voltage. Another solution to correct over-erase is by using positive gate stress on the over-erased cells. However, some over-erased or erratic-erased cells show unstable and unpredictable behavior under positive gate stress. Consequently, they cause over-stress (over-programming) to the erased cells and exhibit operational margin loss during read or erase operations.
U.S. Pat. No. 5,400,286, entitled “Self-Recovering Erase Scheme to Enhance Flash Memory Endurance,” employs only a word line stress for over-erase correction, as shown in FIG. 2. The word line stress is used to narrow the distribution of threshold voltages after an erase of an array of memory. However, this method must conduct a number of loops to stress word lines due to a complex convergence on some over-erased or erratic-erased bits, which consumes a lot of time.
US Patent Publication 2005/0073886, entitled “Memory Device and Method Using Positive Gate Stress to Recover Over-Erased Cell,” provides three methods to solve the over-erased correction. In FIG. 3A, the step of applying positive gate stress is not in the loop of erase verification and thus over-erase situations still likely occur. Therefore, the flow chart suffers from an inefficient soft program operation. Moreover, “apply positive gate stress” at last may cause over-stress issue. The positive gate stress operation corresponding to FN tunneling includes applying a positive gate voltage of, for example, about 8 volts to about 12 volts to all of the wordlines (gate electrodes) simultaneously, while grounding all of the bitlines (sources and drains). The positive gate stress can be applied for a duration between about 1 ms and about 5 seconds. The soft programming of a normal bit is performed by applying a voltage potential (e.g., about 4 volts to about 8 volts), to the gate electrode and a voltage potential (e.g., about 3 volts to 5 volts), to the drain, while grounding or floating the source. In one embodiment, the soft programming is applied as a pulse having a duration between about 0.5 μs and 0.5 sec. In FIG. 3B, the sequence between the steps of applying positive gate stress and hot carrier (HC) soft program is switched. However, because the step of HC soft program is after the step of applying positive gate stress, the drain voltage drops due to over-erased cells induced bit line leakage and thus causes a loss of efficiency. In addition, the flow chart in FIG. 3B still has an unsafe erase-verification loop and may cause an over-stress and induce a loss of sensing margin during a read or erase verification. In FIG. 3C, the flow chart puts the steps of HC soft program and applying positive gate stress in the verification loop and thus the drawbacks of safety concerns in FIGS. 3A and 3B can be eliminated. However, doing so restores the drawback of the flow chart in FIG. 2 which conducts a large number of verification loops and thus wastes a lot of time.
FIG. 4 shows an experiment on the flow chart in FIG. 2. After an erase operation is conducted, the number of bit line leakages is found to be 4523. Then an FN soft program is applied for 40 ms to correct the undesirable over-erased cells. However, the positive gate stress causes the risk of over-programming. Therefore, it is necessary to conduct a second erase operation for 10 ms, and after that it is found that there are 140 bit line leakages in the memory cells. Therefore, a second FN soft program operation is conducted for 40 ms to correct the over-erased cells. In a similar manner, iteration between the erase and verification operations and the FN soft program is continuously conducted and not easy to converge.